Connecting multiple test access port controllers on a single...

Details Connecting multiple test access port controllers on a single... Connecting multiple test access port controllers on a single...

2003-12-15

2008-09-16

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S727000, C714S030000, C714S726000

Reexamination Certificate

active

07426670

ABSTRACT:
Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

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patent: 2002/0184562 (2002-12-01), Nadeau-Dostie et al.
patent: 2005/0050413 (2005-03-01), Whetsel

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