Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-01-30
2007-01-30
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C711S108000, C365S049130
Reexamination Certificate
active
10156532
ABSTRACT:
According to one embodiment of the present invention, a content addressable memory (CAM) device includes a CAM array that includes a plurality of rows of CAM cells each coupled to a corresponding match line, and a test circuit coupled to the match lines that outputs row match results from the match lines onto a match output.
REFERENCES:
patent: 4928260 (1990-05-01), Chuang et al.
patent: 4959811 (1990-09-01), Szczepanek
patent: 5877714 (1999-03-01), Satoh
patent: 6199140 (2001-03-01), Srinivasan et al.
Huse Charles C.
Kavedi Kumaresh
Nataraj Bindiganavale S.
Kerveros James C
Netlogic Microsystems Inc.
Shemwell Mahamedi LLP
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