Address generator for generating addresses for testing a...

Address generator, interleave unit, deinterleaver unit, and...

Address information detecting apparatus and address...

Address parity error processing method, and apparatus and...

Address sequencer within BIST (Built-in-Self-Test) system

Address trap comparator capable of carrying out high speed...

Addressable tap domain selection circuit with TDI/TDO...

Addressing scheme for convolutional interleaver/de-interleaver

Addressing strategy for Viterbi metric computation

Adjustable voltage boundary scan adapter for emulation and test

Advanced bit fail map compression with fail signature analysis

Advanced forward error correction

Algebraic construction of LDPC (Low Density Parity Check)...

Algebraic decoder and method for correcting an arbitrary...

Algebraic geometric code adapted to error bursts

Algebraic low-density parity check code design for variable...

Algebraic soft decoding of reed-solomon codes

Algorithm for a memory-based Viterbi decoder

Algorithm for resynchronizing a bit-sliced crossbar

Algorithm pattern generator for testing a memory device and...