Algorithm pattern generator for testing a memory device and...

Details Algorithm pattern generator for testing a memory device and... Algorithm pattern generator for testing a memory device and...

2007-11-27

2007-11-27

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S738000

Reexamination Certificate

active

11193372

ABSTRACT:
Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component level.

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