Latching annihilation based logic gate
Latching annihilation based logic gate
Latching dynamic logic structure, and integrated circuit...
Latching ECL to CMOS input buffer circuit
Latching input buffer circuit with variable hysteresis
Latching input buffer circuit with variable hysteresis
Latency measurements for wireless communications
Layout architecture and method for fabricating PLDs including mu
Layout area efficient, high speed, dynamic multi-input...
Layout design of integrated circuit, especially datapath circuit
Lead frame with noisy and quiet V.sub.SS and V.sub.DD leads
Leak tolerant low power dynamic circuits
Leakage balancing transistor for jitter reduction in CML to...
Leakage control
Leakage current reduction method
Leakage power management with NDR isolation devices
Leakage sensing and keeper circuit for proper operation of a...
Leakage testing for differential signal transceiver
Leakage-tolerant dynamic wide-NOR circuit structure
Leakage-tolerant keeper with dual output generation...