Layout architecture and method for fabricating PLDs including mu

Details Layout architecture and method for fabricating PLDs including mu Layout architecture and method for fabricating PLDs including mu

1998-10-19

2000-12-05

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326101, 257670, H01L 2500

Patent

active

061572136

ABSTRACT:
A wafer layout architecture and a method for producing multi-device PLDs wherein the wafer layout architecture includes device-linking conductors that allow a wafer to be diced into both single-device chips and multi-device chips. A multi-device chip is a single chip that includes two or more discrete PLD circuits that are connected by the device-linking conductors. Each device-linking conductor is formed on the wafer and extends across a scribe line space separating two discrete FPGA circuits. When the two discrete FPGA circuits are separated during a dicing process, the wafer is cut along the scribe line space and the device-linking conductor is severed. When a multi-device chip is formed that includes both of the discrete FPGA circuits, the device-linking conductor is selectively implemented using programmable switches to provide a signal path between the two discrete FPGA circuits. Because the device-linking conductors are formed on the chip, the device-linking conductors provide on-chip signal transmissions having substantially less delay than off-chip signal transmission methods.

REFERENCES:
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5696404 (1997-12-01), Murari et al.
patent: 5767565 (1998-06-01), Reddy
Michael Adler, "GE High Density Interconnect: A Solution to the System Interconnect Problem", General Electric, Corporate Research and Development, Schenectady, NY, publication date believed to be Aug. 26, 1991.

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