Leak tolerant low power dynamic circuits

Details Leak tolerant low power dynamic circuits Leak tolerant low power dynamic circuits

1997-02-20

1998-11-03

Tokar, Michael J.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 28, 326121, H03K 190948, H03K 19096

Patent

active

058314520

ABSTRACT:
A novel precharge circuit is provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.

REFERENCES:
patent: 4080539 (1978-03-01), Stewart
patent: 5065048 (1991-11-01), Asai et al.
patent: 5126596 (1992-06-01), Millman
patent: 5400295 (1995-03-01), Matsumura et al.

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