Leakage-tolerant dynamic wide-NOR circuit structure

Details Leakage-tolerant dynamic wide-NOR circuit structure Leakage-tolerant dynamic wide-NOR circuit structure

2006-09-19

2006-09-19

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S119000

Reexamination Certificate

active

07109757

ABSTRACT:
One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.

REFERENCES:
patent: 6404235 (2002-06-01), Nowka et al.
patent: 6549040 (2003-04-01), Alvandpour et al.
patent: 6714059 (2004-03-01), Choe
patent: 6791365 (2004-09-01), Bosshart
patent: 6914452 (2005-07-01), Gauthier et al.
patent: 6940314 (2005-09-01), Bloker et al.
patent: 2004/0263208 (2004-12-01), Levy et al.

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