Leakage balancing transistor for jitter reduction in CML to...

Details Leakage balancing transistor for jitter reduction in CML to... Leakage balancing transistor for jitter reduction in CML to...

2007-03-06

2007-03-06

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S062000, C326S063000, C326S064000, C326S065000, C326S066000, C326S067000, C326S068000, C326S080000, C326S081000, C326S082000, C326S084000, C326S085000, C326S086000, C326S087000, C326S112000, C326S113000, C326S114000, C326S115000, C326S126000, C326S127000, C327S052000, C327S065000

Reexamination Certificate

active

11168034

ABSTRACT:
The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

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