Latching annihilation based logic gate

Details Latching annihilation based logic gate Latching annihilation based logic gate

2001-11-20

2003-06-24

Le, Don (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S098000, C326S108000

Reexamination Certificate

active

06583650

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to digital computing systems, and more specifically to precharge devices.
BACKGROUND
Precharge devices are synchronous logic circuits that generate an output depending upon a predetermined combination of inputs for implementing a logical function. Two common uses for precharge devices are as decoders and as comparators. Decoders output a unique signal (high or low) if and only if all of the bits of an input match a predetermined set of values. A decoder may thereby enable a particular write line in a matrix of memory cells if and only if an input memory address matches the predetermined address of a line of memory cells to which the decoder is connected. Similarly, a comparator will output a unique signal if and only if two inputs, each containing multiple data bits, are identical.
Precharge devices are characterized by two states, precharge and evaluate. In the precharge state, a node is charged to a known or predetermined voltage level. In the evaluate state, an array or “tree” of transistors configured in a basic logical function (e.g., NAND, NOR) is given the opportunity to discharge the node to a second known or predetermined voltage level or to allow the charge to persist. The logical function input signals are connected, typically, to the gates of one or more of the transistors in the logical section tree. The final charge on the node may thereby be controlled by the particular values of the inputs. The final voltage at the node, high or low, acts as the output of the precharge device after being suitably buffered and, perhaps, inverted.
Two basic logical section structures include stacked NAND and parallel NOR structures. In a stacked NAND logical section, two or more transistors are stacked in series with one another and to the precharge node. The precharged node is discharged if and only if all of the transistor gate inputs are active (e.g., high). With the parallel NOR configuration, two or more transistors are arranged in parallel with one another and across the precharged node. If any of the transistor gate inputs are active, the precharge node is discharged. In other words, the precharged node is not discharged if and only if all of the transistor gate inputs are not active. Of course, with the use of inverted or non-inverted inputs, any logical function such as a decoder may be implemented with either structure. An important concept to be understood with precharged circuits however, is monotonicity. This is a property of a signal such that it may only transition in a single direction (i.e., high to low, or low to high) during the evaluate portion of the cycle. Monotonic circuits are reset to the default value during the precharge portion of the cycle. For example, the output of a precharged NOR gate with inverted input is indeed a logical AND, but the output will have the wrong direction of transition and therefore will be unsuitable as an input to other monotonic precharged gates. For additional information relating to precharge devices, reference may be made to U.S. Pat. No. 5,291,076 to Bridges et al (“Bridges”).
In high performance applications with complicated functions that require numerous inputs, the stacked NAND structure may not be practical because the time required for discharging through a relatively large stack of transistors can be prohibitive. In fact, it is usually not feasible to use stacks of more than four transistors. Thus, the parallel NOR structure is favored. However, the primary problem with NOR structures is that for monotonic logic, they can only compute OR functions, not AND functions since inverters are necessary to achieve the correct logical sense. The Bridges reference disclosed a parallel NOR device with a screening transistor, which in effect, screens the charged node of the parallel NOR section from the output section and creates a separate charged node that discharges when the parallel charged node is to persist and persists when the parallel charged node is to discharge. Bridges also disclosed a precharge device with latching transistors for improving the device's resistance to inherent circuit instabilities. Unfortunately, neither the Bridges design (nor any other design known of in the prior art) did anything for unstable logic inputs. Separate latches are needed for each input to ensure that it is sufficiently stable to ensure that the precharge output properly reflects the input states when the circuit goes from the precharge to the evaluate phase.
Accordingly, what is needed is an improved circuit that is capable of providing a stable output without the need for stable inputs throughout the evaluation phase.
SUMMARY OF THE INVENTION
These and other objects, features and technical advantages are achieved by a system and method which the present invention provides a precharge circuit that has a first precharged node, a second precharged node, and a latch device. The first precharged node is charged to a high value during a precharge state. In response to a transition from the precharge state to an evaluate state, it either discharges to a low value or remains charged at its high value. The second precharged node has a value in the evaluate state that is based on the value of the first precharged node upon the circuit transitioning to the evaluate state. The latch device is connected to the second precharged node for latching this value in the evaluate state. With the latching device, this value is not affected by the first precharged node once the circuit has sufficiently transitioned to the evaluate state.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.


REFERENCES:
patent: 3935474 (1976-01-01), Komarek
patent: 4700086 (1987-10-01), Ling et al.
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5291076 (1994-03-01), Bridges et al.
patent: 5831452 (1998-11-01), Nowak et al.
patent: 5903169 (1999-05-01), Kong
patent: 5990706 (1999-11-01), Matsumoto et al.
patent: 6043696 (2000-03-01), Klass et al.
patent: 6052008 (2000-04-01), Chu et al.
patent: 6121796 (2000-09-01), Ciraula et al.
patent: 6172531 (2001-01-01), Aipperspach et al.
patent: 6184718 (2001-02-01), Tran et al.
patent: 04372222 (1992-12-01), None
U.S. patent application Ser. No. 09/561,081, Arnold, filed Apr. 28, 2000.

Affiliated with

Also associated with

Rating

Latching annihilation based logic gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latching annihilation based logic gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latching annihilation based logic gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3106799