Leakage power management with NDR isolation devices

Details Leakage power management with NDR isolation devices Leakage power management with NDR isolation devices

2005-10-07

2008-08-26

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S082000, C326S033000

Reexamination Certificate

active

07417451

ABSTRACT:
A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

REFERENCES:
patent: 6208171 (2001-03-01), Kumagai et al.
patent: 6242948 (2001-06-01), Makino
patent: 6285213 (2001-09-01), Makino
patent: 6512274 (2003-01-01), King et al.
patent: 6556071 (2003-04-01), Notani et al.
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patent: 2002/0057123 (2002-05-01), King
“Circuit Techniques for Gate and Sub-Threshold Leakage Minimization in Future CMOS Technologies”, Rahul Rao, Jeffrey Burns, and Richard Brown, European Solid-State Circuits Conference (ESSCIRC 2003) (Sep. 16-18, 2003).

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