Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
2008-12-01
2010-12-14
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C326S112000, C326S119000
Reexamination Certificate
active
07852113
ABSTRACT:
In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node.
REFERENCES:
patent: 6166985 (2000-12-01), McDaniel et al.
patent: 6307396 (2001-10-01), Mulatti et al.
patent: 7227804 (2007-06-01), Kothandaraman et al.
patent: 2002/0158665 (2002-10-01), Ye et al.
patent: 2005/0146948 (2005-07-01), Hose, Jr. et al.
patent: WO 00/67380 (2000-11-01), None
Terzioglu Esin
Winograd Gil I.
Haynes & Boone LLP.
Novelics, LLC.
Tran Anh Q
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