Leakage current reduction method

Details Leakage current reduction method Leakage current reduction method

2005-10-18

2005-10-18

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S017000, C326S112000, C326S119000

Reexamination Certificate

active

06956398

ABSTRACT:
The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

REFERENCES:
patent: 6864708 (2005-03-01), Takahashi et al.
patent: 2001/0013806 (2001-08-01), Notani

Affiliated with

Also associated with

Rating

Leakage current reduction method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Leakage current reduction method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leakage current reduction method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3439871