Independent timing compensation of write data path and read data

Details Independent timing compensation of write data path and read data Independent timing compensation of write data path and read data

1998-03-25

2000-10-03

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

713503, G06F 112

Patent

active

061287482

ABSTRACT:
An apparatus includes a read clock path to provide a read clock signal to a memory controller, wherein the read clock signal is to control timing of a memory controller when reading from a memory. The apparatus also includes a write clock path, independent of the read clock path, to provide a write clock signal to the memory controller, wherein the write clock signal is to control timing of the memory controller when writing to the memory.

REFERENCES:
patent: 5448715 (1995-09-01), Lelm et al.
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5889726 (1999-03-01), Jeddeloh
patent: 5926838 (1999-07-01), Jeddeloh

Affiliated with

Also associated with

Rating

Independent timing compensation of write data path and read data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Independent timing compensation of write data path and read data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Independent timing compensation of write data path and read data will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-205892