Interleaved delay line for phase locked and delay locked loops

Details Interleaved delay line for phase locked and delay locked loops Interleaved delay line for phase locked and delay locked loops

2006-03-28

2006-03-28

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S500000, C713S503000, C713S600000, C327S149000, C327S152000, C327S153000, C327S158000, C327S182000, C307S141000, C307S409000, C365S194000, C365S233100, C370S509000, C370S517000, C370S519000

Reexamination Certificate

active

07020794

ABSTRACT:
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

REFERENCES:
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5192886 (1993-03-01), Wetlaufer
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 5638010 (1997-06-01), Adams
patent: 5844954 (1998-12-01), Casasanta et al.

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