Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-01-05
2001-07-24
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C710S107000
Reexamination Certificate
active
06266777
ABSTRACT:
BACKGRQUND OF THE INVENTION
This invention relates to an information processing apparatus and more particularly to an information processing apparatus which includes a bus on which data exist for a predetermined time after a request is issued.
Referring to
FIG. 16
, a conventional information processing apparatus of this type comprises a plurality of processing units (hereinafter referred to as PU)
1611
, . . . , and
1612
, a main memory unit (hereinafter referred to as MM)
1613
comprising a plurality of memory units (hereinafter referred to as a bank) shared by the PUs, a system bus (hereinafter referred to as bus)
1614
connecting these units and a control line
1615
for connecting the PUs to each other.
In bus
1614
, the transmission performance of an interface between a PU and the bus is equal to that of an interface between the bus and the MM. The transmission performance of a bank interface in the MM depends on the operating time of a memory element. A bus cycle has an address cycle for sending out a request field containing operating instructions (hereinafter referred to as RQ) on the bus and an address field that is referred to during a memory access, and a data cycle for transmitting data. The bus is operated according to a pipeline method. In the bus, data (hereinafter referred to as response data) corresponding to a RQ is transferred in a predetermined time after a RQ is issued. Hereinafter, the time interval, from the time a RQ is issued until data is transmitted, is referred to as latency. In an interval between the time a RQ is issued and the data is transmitted, the bus is kept open so that another RQ can be executed during this time.
A control line
1615
is used for transmitting cache status information existing in an arithmetic operating unit in its own PU to all other PUs answering a RQ issued to the bus. Control line
1615
also transmits a type of the RQ from its own PU to all other PUs in order to maintain cache coherence in the system for mediating competition for each PU to use bus
1614
. The cache coherency protocol utilizes a snoop system.
A transmission control unit
1623
comprises: a CPU connecting element
1631
, having an interface with the CPU, and for carrying out data transmission between the CPU and the transmission control unit; a bank busy management element
1632
for controlling access of the MM to the bank that determines whether an access is enabled upon issuing a RQ for accessing the bank; a bus competition mediating element
1634
for mediating a request for issuing a RQ to the bus through control line
1615
from each PU connected to the bus and providing any PU with a privilege of use of the bus; a bus connecting element
1635
having an interface with the bus that carries out data transmission between the bus and transmission contrail unit
1623
; and a RQ transmission control element
1636
for controlling CPU connecting element
1631
bank busy management element
1632
, bus competition mediating element
1634
and bus connecting element
1635
.
In timing charts described below, cycle A is a bus address cycle and cycle D is a and data cycle.
According to
FIG. 8
, at time 0, a read RQ is processed in the PU and, at time 2, the RQ is issued to the bus. At time 4, the RQ is processed in the MM and, in an interval from time 6 to time 10, the bank is accesed. At time 11, the MM reads out data corresponding to the RQ from the bank and, at time 13, the data is transmitted in the MM. At time 15, the data is sent out to the bus and, at time 17, the PU receives the data. The latency on the bus until data is transmitted after the RQ is issued is time 12.
In FIG, IT, at time 0, a write RQ is processed in the PU and at time 2, the RQ is issued to the bus. In an interval from time 4 to time 12, the RQ is maintained to wait for data in the MM and in an interval from time 14 to time 18, the MM accesses the bank of the RQ. At time 13, the write data is transmitted within the PU and at time 15, the data is transmitted to the bus. At time 17, the data is transmitted within the MM and at time 19, the data is written into the bank. The latency on the bus until data is transferred after the RQ is issued is time 12 as in the read operation.
FIG. 18
is a time chart showing data transmission operation (hereinafter referred to as C write) between caches when the read address of a certain CPU to the memory dirty-hits a cache of another CPU. Cycles A and D represent bus address and data cycles, respectively. RQ represents a read RQ. Data represents response data of that RQ. Latency represents bus latency.
From time 0 to time 17 the operation is the same as in FIG.
8
. As a result of snooping of the bus, an address requested by the read RQ dirty-hits a CPU cache in another PU, and then a RQ (C write RQ) for data transmission between caches, from the dirty-hit CPU to the CPU which issued the read RE is generated. At time he, the C write RQ is processed in the PU having a dirty-hit CPU and at time 20, the RQ is issued. At time 22, the RQ is processed in the PU which issued the read RQ and at time 33, the data is transmitted to the bus. At time 35, the data is transmitted within the PU which issued the read RQ. The bus latency until corresponding data is transmitted after the RQ is issued is time 12 as in the read operation and write operation.
In the conventional information processing apparatus;, according to timing charts of
FIGS. 8
,
17
and
18
, there is a predetermined latency between the RQ and data. This is common with these kinds of RQs, therefore he latency affects system performance.
A problem with the above described conventional information processing apparatus, is that the latency deteriorates the performance of the write operation to the memory.
Another problem, which arises when transmitting data between caches, is deterioration of the data transmission performance between the caches. This is because the latency of the bus causes a time interval from an issuance of address information to data transmission destination from the CPU until the appearance of transmission data. The delay of the transmission data between caches causes a problem because the operation of the CPU to receive the transmitted data stops.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an information processing apparatus in which the latency of the bus is variable and which uses the bus effectively.
According to one aspect of the present invention, there is provided an information processing apparatus which comprises: a bus having latency; a first element which sends out a request to the bus, wherein the request includes information showing the time that data corresponding to the request exists on the bus; a second element which sends out the data to the bus at the time; a third element which receives the request and identifies a time during which the data exists on the bus; and a fourth element which receives the data in accordance with the time which the element identifies.
According to another aspect of the present invention, there is provided an information processing apparatus which comprises: a bus having latency; a first means for sending out a request to the bus, wherein the request includes information showing the time that data corresponding to the request exists on the bus; a second means for sending out the data to the bus at the time; a third means for receiving the request and identifying a time during which the data exists on the bus and a fourth means for receiving the data in accordance with the time which the element identifies.
According to another aspect of the present invention, there is provided an information processing apparatus which comprises: a bus on which data exist for a predetermined time after the issuance of a request; a processing element which controls an interval for transmitting data and sends out the data to the bus based on the interval; and a storage element which receives the data.
According to another aspect of the present invention, there is provided an information processing met
Heckler Thomas M.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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