Integrated circuit memory architecture with selectively...

Details Integrated circuit memory architecture with selectively... Integrated circuit memory architecture with selectively...

2006-05-02

2006-05-02

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000

Reexamination Certificate

active

07039822

ABSTRACT:
An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

REFERENCES:
patent: 5663921 (1997-09-01), Pascucci et al.
patent: 6446249 (2002-09-01), Wang et al.
patent: 6658523 (2003-12-01), Janzen et al.

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