Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2006-06-20
2006-06-20
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C712S219000, C712S245000
Reexamination Certificate
active
07065665
ABSTRACT:
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
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Bose Pradip
Cook Peter W.
Jacobson Hans M.
Kudva Prabhakar N.
Schuster Stanley E.
Browne Lynne H.
Karra, Esq. Satheesh K.
Law Office of Charles W. Peterson, Jr.
Patel Anand B.
Percello, Esq. Louis J.
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