Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-12-06
2005-12-06
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S013000, C712S015000
Reexamination Certificate
active
06973559
ABSTRACT:
A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.
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Deneroff Martin M.
Passint Randal S.
Thorson Gregory M.
Chan Eddie
Meonske Tonia L.
Silicon Graphics Inc.
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