Scalable hypercube multiprocessor network for massive...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S013000, C712S015000

Reexamination Certificate

active

06973559

ABSTRACT:
A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

REFERENCES:
patent: 4860201 (1989-08-01), Stolfo et al.
patent: 5113523 (1992-05-01), Colley et al.
patent: 5133073 (1992-07-01), Jackson et al.
patent: 5263124 (1993-11-01), Weaver et al.
patent: 5434972 (1995-07-01), Hamlin
patent: 5471580 (1995-11-01), Fujiwara et al.
patent: 5586258 (1996-12-01), Conterno et al.
patent: 5625836 (1997-04-01), Barker et al.
patent: 5669008 (1997-09-01), Galles et al.
patent: 5878241 (1999-03-01), Wilkinson et al.
patent: 6041358 (2000-03-01), Huang et al.
patent: 6230252 (2001-05-01), Passint et al.
patent: 6334177 (2001-12-01), Baumgartner et al.
patent: 99/26429 (1999-05-01), None
Laudon, James and Daniel Lenoski, The SGI Origin: A ccNUMA Highly Scalable Server, 1997, ISCA of the ACM, Denver, CO., pp. 241-251.
Kumar, J. Mohan and Patnaik, L. M., “Extended Hypercube: A Heirarchical Interconnection Network of Hypercubes,” Jan. 1992, IEEE Transactions on Parallel and Distributed Systems, vol. 3, No. 1.
Goodman, James R. and Sequin, Carlo H., “Hypertree: A Mulitprocessor Interconnection Topology,” Dec. 1981, IEEE Transactions on Computers, vol. C-30, No. 12.
Efe, Kemal and Ramaier, Kumar, “Congestion and Fault Tolerence of Binary Tree Embeddings on Hypercube,” 1999, IEEE.
Nishi, H., et al., “The JUMP-1 Router Chip: A versatile router for supporting a distributed shared memory”,Proceedings of the 1996 IEEE 15th Annual Int'l Phoenix Conference on Computers & Communication, Conf. 15, XP000594785,pp. 158-164, (Mar. 1996).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Scalable hypercube multiprocessor network for massive... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scalable hypercube multiprocessor network for massive..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable hypercube multiprocessor network for massive... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3500188

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.