Scalable processor

Details Scalable processor Scalable processor

2005-12-20

2005-12-20

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C712S219000

Reexamination Certificate

active

06978360

ABSTRACT:
A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

REFERENCES:
patent: 6006325 (1999-12-01), Burger et al.
patent: 6092158 (2000-07-01), Harriman et al.
patent: 6647489 (2003-11-01), Col et al.
patent: 6671747 (2003-12-01), Benkual et al.

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