Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2005-09-27
2005-09-27
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S219000, C712S245000
Reexamination Certificate
active
06950925
ABSTRACT:
A microprocessor may include several execution units and a scheduler coupled to issue operations to at least one of the execution units. The scheduler may include several entries. A first entry may be allocated to a first operation. The first entry includes a source status indication for each of the first operation's operands. Each source status indication indicates whether a value of a respective one of the first operation's operands is speculative. The scheduler is configured to update one of the first entry's source status indications to indicate that a value of a respective one of the first operation's operands is non-speculative in response to receiving an indication that a value of a result of a second operation is non-speculative.
REFERENCES:
patent: 5452426 (1995-09-01), Papworth et al.
patent: 5511172 (1996-04-01), Kimura et al.
patent: 5584001 (1996-12-01), Hoyt et al.
patent: 5966544 (1999-10-01), Sager
patent: 6094717 (2000-07-01), Merchant et al.
patent: 6185668 (2001-02-01), Arya
patent: 6205542 (2001-03-01), Grochowski et al.
patent: 6212626 (2001-04-01), Merchant et al.
patent: 6564315 (2003-05-01), Keller et al.
patent: 2001/0010073 (2001-07-01), Janik et al.
patent: 03/093983 (2003-11-01), None
International search report application number PCT/US 03/22696 mailed Feb. 18, 2004.
Eric Rotenberg, “Trace Processors: Exploiting Hierarchy and Speculation,” 1999, 69 pages.
Toshinori Sato, “Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Sheduling Structure,” 1999, 8 pages.
T. Sato, et al., “Comprehensive Evaluation of an Instruction Reissue Mechanism,” IEEE, 2000 International Symposium on Parallel Architectures, Algorithms and Networks, Dec. 7, 2000, 9 pages.
Mikko H. Lipasti, et al., “Exceeding the Dataflow Limit via Value Prediction,” Proceedings of the 29thAnnual ACM/IEEE International Symposium on Microarchitecture, Dec. 2-4, 1996, 12 pages.
David M. Gallagher, et al., “Dynamic Memory Disambiguation Using the Memory Conflict Buffer,” Appeared in ASPLOS-VI Proceedings, Oct. 1994, 13 pages.
Mikko H. Lipasti, et al., “Value Locality and Load Value Prediction,” Reprint of paper to appear in ASPLOS-VII, Oct. 1996, 10 pages.
Brad Calder, et al., “A Comparative Survey of Load Speculation Architectures,” Journal of Instruction-Level Parallelism I (2000), pp. 1-39.
Glenn Reinman, et al., “Predictive Techniques for Agressive Load Speculation,” Published in the Proceedings of the Annual 31stInternational Symposium on Microarchitecture, Dec. 1998, 11 pages.
Alsup Mitchell
Filippo Michael
Sander Benjamin T.
Advanced Micro Devices , Inc.
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Pan Daniel H.
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