Scannable zero-catcher and one-catcher circuits for reduced...

Electrical computers and digital processing systems: processing – Processing architecture

Reexamination Certificate

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Details

C711S105000

Reexamination Certificate

active

06697929

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits and computer systems, and more specifically to scannable zero-catcher and one-catcher circuits.
BACKGROUND OF THE INVENTION
In recent years, the price of personal computers (PCs) has rapidly declined. As a result, more and more consumers have been able to take advantage of newer and faster machines. Users in both the business and home markets are now purchasing computers for a variety of uses. Numerous peripheral devices, expansion boards, and add-on cards are also available for system upgrades.
As the technology in computer systems improves, so has the complexity of the circuitry. This is especially true in the processor realm. The number of transistor devices present on a single silicon die has grown exponentially from only thousands in the 1980s to millions today. As the number of circuits and transistors increase, it becomes much more difficult for design engineers to test and debug such large circuits and integrated circuit devices.
During debug, engineers often try to take snapshots of the system or circuit that is under test. Such snapshots may provide some insight into the current state of the overall device or help narrow down a problem area. Engineers can evaluate this data and determine the cause of an error. In order to take read out the values of circuit nodes and signals, the circuit needs to have a way to send these values from latches or other storage devices in the circuit to the outside world.
However, not all integrated circuits are designed to include such testing support. Many of today's integrated circuits use some latch type memory mechanism to store data internally. These mechanisms do not provide a way for a user to read the contents or to send the contents out to a tester. Nor do these mechanisms allow a user to program or set these latches to a particular value.


REFERENCES:
patent: 5041742 (1991-08-01), Carbonaro
patent: 5867036 (1999-02-01), Rajsuman
patent: 5870411 (1999-02-01), Durham et al.
patent: 6091261 (2000-07-01), De Lange
patent: 6473354 (2002-10-01), Noda et al.
patent: 6483363 (2002-11-01), Karnik et al.
patent: 6529861 (2003-03-01), Patra et al.

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