Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2011-08-09
2011-08-09
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S228000
Reexamination Certificate
active
07996663
ABSTRACT:
A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectural state is saved to memory in response to a save state triggering event, which may include a hardware event or a software event. Once saved, the state is potentially transferred to another processing element, such as a second core. As a result, hardware, software, or combination thereof may transfer architectural states between multiple processing elements, such as threads or cores, of a processor utilizing hardware support.
REFERENCES:
patent: 5926646 (1999-07-01), Pickett et al.
patent: 6212609 (2001-04-01), Bennett et al.
patent: 6223208 (2001-04-01), Kiefer et al.
patent: 6516395 (2003-02-01), Christie
patent: 6671762 (2003-12-01), Soni et al.
patent: 6810476 (2004-10-01), McGrath et al.
patent: 7130977 (2006-10-01), Christie et al.
patent: 7209994 (2007-04-01), Klaiber et al.
patent: 7254744 (2007-08-01), Dunston
patent: 7487502 (2009-02-01), Wang
patent: 7500049 (2009-03-01), Dixon
patent: 7631307 (2009-12-01), Desai et al.
patent: 7707341 (2010-04-01), Klaiber et al.
patent: 7778271 (2010-08-01), Day et al.
patent: 2003/0033507 (2003-02-01), McGrath
patent: 2003/0110012 (2003-06-01), Orenstien et al.
patent: 2004/0019771 (2004-01-01), Quach
patent: 2004/0098429 (2004-05-01), Crispin et al.
patent: 2004/0123201 (2004-06-01), Nguyen et al.
patent: 2005/0223199 (2005-10-01), Grochowski
patent: 2007/0079150 (2007-04-01), Belmont et al.
Kumar, R, etal., Single-ISA Heterogeneous Muiti-Core Architectures: The Potential for Processor Power Reduction, 2003, Proceeding of the 36th Intl, Symposium on Microarchitecture, IEEE, 12 pages.
Shateyesteh, A, etal., Reducing the Latency and Area Cost of Core Swapping through Helper Engines,2005, Proceeding of the 2005 Intl. Conference on Computer Design, IEEE, 7 pages.
Kursun, E. etal., Low Overhead Core Swapping for Thermal Management, 2005, Springer-Verlag, pp. 46-57.
Iacobovici Sorin
Iskarous Moenes
Stillwell, Jr. Paul M.
Coleman Eric
Intel Corporation
McAbee David P.
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