Scheduling instructions in a cascaded delayed execution...

Details Scheduling instructions in a cascaded delayed execution... Scheduling instructions in a cascaded delayed execution...

2006-02-09

2008-11-04

Huisman, David J (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

C712S215000

Reexamination Certificate

active

07447879

ABSTRACT:
A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group is a load instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.

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Shen et al., “Modern Processor Design—Fundamentals of Superscalar Processors,” 2004, p. 185.
Yoaz et al., “Speculation Techniques for Improving Load Related Instruction Scheduling,” 1999, 12 pages.

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