Processor with a processor-accessible cache for data received fr
Processor with a replay system that includes a replay queue...
Processor with conditional execution of every instruction
Processor with conditional instruction execution based upon...
Processor with coprocessor interfacing functional unit for...
Processor with dependence mechanism to predict whether a...
Processor with different width functional units ignoring...
Processor with enhanced instruction set
Processor with improved history file mechanism for restoring...
Processor with instruction qualifiers to control MMU operation
Processor with instructions that operate on different data...
Processor with instructions that operate on different data...
Processor with internal memory configuration
Processor with memory access stage adapted to fetch an...
Processor with multiple execution pipelines using pipe stage sta
Processor with multiple execution units and local and global reg
Processor with multiple-thread, vertically-threaded pipeline
Processor with N adders for parallel target addresses...
Processor with pipeline conflict resolution using...
Processor with pointer tracking to eliminate redundant...