Processor with multiple execution pipelines using pipe stage sta

Details Processor with multiple execution pipelines using pipe stage sta Processor with multiple execution pipelines using pipe stage sta

1997-07-29

2000-10-24

Lim, Krisna

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712214, G06F 900, G06F 1130

Patent

active

061382302

ABSTRACT:
A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.

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