Processor with memory access stage adapted to fetch an...

Details Processor with memory access stage adapted to fetch an... Processor with memory access stage adapted to fetch an...

2011-06-07

2011-06-07

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction fetching

C711S100000, C710S005000

Reexamination Certificate

active

07958333

ABSTRACT:
A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memory access stage. The memory access stage includes logic adapted to detect whether a memory access operation is defined in each issued instruction, and to fetch another instruction if no memory access operation is detected.

REFERENCES:
patent: 7506140 (2009-03-01), Jensen
patent: 2004/0098496 (2004-05-01), Wolrich et al.
patent: 2007/0143581 (2007-06-01), Mansell
patent: 1499978 (2005-01-01), None
patent: 1555610 (2005-07-01), None
patent: 9522103 (1995-08-01), None
International Search Report dated Oct. 9, 2008.

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