Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2000-02-04
2003-07-01
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S228000, C712S244000, C714S015000, C714S016000
Reexamination Certificate
active
06587941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to pipelined microprocessor architecture and, in particular, to a pipelined microprocessor utilizing a history file mechanism to support speculative execution of instructions while maintaining a precise state.
2. Description of the Related Art
Microprocessors execute sequences of instructions. For many of these instructions, execution can be partitioned into an operation that produces the correct result in most cases while computing an exception condition that indicates the validity of the aforementioned result. Examples of such instructions include: (1) branch instructions, where branch prediction yields the “mostly correct” answer, and branch evaluation later computes the validity of the prediction, (2) load instructions, where a cache may provide data, and a memory management unit separately computes the validity of the data, and (3) arithmetic instructions, where an overflow condition maybe computed separately from the result. An instruction has “finished” executing when dependent instructions can proceed, whereas an instruction can be “committed” (or “completed”) when it has finished and it, and all previous instructions, did not result in an exception condition.
Instruction set architectures (ISAs) tend to hide the exception conditions from the programmer, that is, the instruction definition either does not mention the exception cases, or requires a well-defined action. Hence, a branch is always expected to evaluate correctly, and a load instruction is expected to succeed, even if the data is not cached. An overflow condition may require the next instruction fetched to be a special one, such as a trap or handler.
Because the ISA hides the exceptions, processor designers generally have two choices: either fully resolve the instructions, including the exception cases, before scheduling the next instruction, or speculatively, without regard to exception conditions, execute instructions which requires including a mechanism for recovering the machine state for every instruction that has finished but not committed and that might except. If such a mechanism is present, the machine is said to support precise exceptions. Precise exceptions are exceptions where the cause of the exception is known and where the state of the processor when the exception occurred was saved.
Fundamentally, the state of the processor is lost when it is overwritten. To support precise exceptions, processor state should be lost only when it is overwritten by an instruction that has committed. A variety of mechanisms have been devised that achieve this. A reorder buffer buffers results of instructions that have finished, but not committed. Register renaming uses a larger set of physical registers and a variable mapping from architectural registers to physical registers. Mappings and their corresponding set of physical registers are conserved until overwritten by instructions that commit.
Another approach is a history file unit. This approach lets finishing instructions which have not committed overwrite the architectural values while keeping a copy of the old, overwritten values so that the prior state of the processor can be retrieved. When results are written to a register file, the old data of the registers is read and transferred to the history. When an exception occurs, data is transferred from the history file unit and restored to the register file in a last-in first-out manner. The history file unit has several disadvantages, however. For example, additional read ports are required on the register file to read the registers which are being overwritten. An additional disadvantage is that processor cycles are lost while prior values are restored on an exception.
Therefore a need exists for a pipelined processor utilizing an improved history file unit mechanism to support speculative execution of instructions while maintaining a precise state without adding additional read ports to a register file or devoting processor cycle solely to restoring old values on an exception.
SUMMARY OF THE INVENTION
A pipelined processor and method are disclosed including an improved history file unit. The pipelined processor processes a plurality of instructions in order. A register file is included which includes a different read port coupled to each register field in an instruction buffer for reading data from the register file. A history file unit is included and is coupled to each of the read ports of the register file for receiving a copy of all data read from the register file.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
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Implementing precise interrrupts in pipelined processors, Smith, J.E.; Pleszkun, A.R., Computers, IEEE Transactions on, vol.: 37 Issue: 5, May 1988 pp.: 562-573.*
Tamir, Y.; Tremblay, M.; Rennels, D.A., The implementation and application of micro rollback in fault-tolerant VLSI systems, Fault-Tolerant Computing, 1988. FTCS-18, Digest of Papers., Eighteenth International Symposium on, 1988 pp.: 234-239.*
Wang, C.-J.; Emnett, F., Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods, Computers and Digital Techniques, IEEE Proceedings, vol.: 140 Issue: 4, Jul. 1993 pp.: 196-199.
Flacks Brian King
Hofstee Harm Peter
Takahashi Osamu
Bracewell & Patterson L.L.P.
Chan Eddie
Collins Scott M.
International Business Machines - Corporation
Salys Casimer K.
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