Processor with multiple execution units and local and global reg

Details Processor with multiple execution units and local and global reg Processor with multiple execution units and local and global reg

1999-03-30

2000-07-11

Eng, David Y.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

G06F 1516

Patent

active

060887842

ABSTRACT:
A method and an apparatus for data processing between multiple execution units using local and global register bypasses is disclosed. In one embodiment, the device contains a register file, at least two bypass circuits, a plurality of execution units, and a control circuit. Each bypass circuit connects to at least one execution unit. The control circuit, which is coupled to the execution units, limits no more than one clock delay per each execution clock cycle. The control circuit further designates delay clock cycles for handling delays.

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