Processor with a processor-accessible cache for data received fr

Details Processor with a processor-accessible cache for data received fr Processor with a processor-accessible cache for data received fr

1993-09-15

2000-05-16

Maung, Zarni

Electrical computers and digital processing systems: processing

Processing control

711113, G06F 738

Patent

active

060651113

ABSTRACT:
A processor for a multiprocessor system, such as a parallel processor system, connected to a network has a sending unit and a receiving unit for transferring and receiving data to and from the network as well as a receive cache and a main cache. When data is received from the network, it is determined whether a hit or miss occurs to the main cache and receive cache, respectively. If a hit to the receive cache occurs, then the receive cache controller stores the data directly in the receive cache as it is received. When a hit to the main cache occurs, an intercache transfer is executed for transferring the hit block in the main cache to the receive cache so that the data can be stored in the receive cache. When an instruction processor requests access to data held in the receive cache, the data is retrieved to the instruction processor and at the same time transferred to a main cache.

REFERENCES:
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4942518 (1990-07-01), Weatherford et al.
patent: 5155832 (1992-10-01), Hunt
patent: 5247648 (1993-09-01), Watkins et al.
patent: 5249282 (1993-09-01), Segers
patent: 5251310 (1993-10-01), Smelser et al.
Electronic Information Communiations Society, Collection of Papers, D-1, vol. J75-D-1, No. 8, pp. 637-645, 1992.

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