Instruction redefinition using model specific registers
Instruction result labeling in a counterflow pipeline processor
Instruction rollback processor system, an instruction...
Instruction scheduling system of a processor
Instruction segment filtering scheme
Instruction set and executing method of the same by...
Instruction set extension using operand bearing NOP...
Instruction set extension using prefixes
Instruction set for bi-directional conversion and transfer...
Instruction set for bi-directional conversion and transfer...
Instruction set for bi-directional conversion and transfer...
Instruction specified register value saving in allocated...
Instruction template for efficient processing clustered...
Instruction translation system and method achieving...
Instruction vector-mode processing in multi-lane processor...
Instruction-issuing circuit that sets reference dependency...
Instruction-level multithreading according to a...
Instruction-parallel processor with...
Instruction-programmable processor with instruction loop cache
Instruction/skid buffers in a multithreading microprocessor...