Instruction redefinition using model specific registers

Details Instruction redefinition using model specific registers Instruction redefinition using model specific registers

1997-07-17

2000-06-13

Ellis, Richard L.

Electrical computers and digital processing systems: processing

Processing control

Instruction modification based on condition

712229, 712209, G06F 9318

Patent

active

060761563

ABSTRACT:
A microprocessor employs an instruction redefinition register which programmably redefines the operation performed by one or more instructions. Instructions may be added to the instruction set executed by the microprocessor without consuming opcode encodings. One or more new instructions may be mapped to an opcode assigned to a redefinable instruction (e.g. a seldom-used instruction selected during the design of the microprocessor to be redefinable to one or more of the added instructions). A particular application program may select the architecturally defined operation corresponding to the redefinable instruction or one of the operations corresponding to the new operations by coding the instruction redefinition register. In one particular embodiment, the instruction redefinition register is a model specific register (MSR) as defined by the x86 microprocessor architecture. A frequently-used instruction may also be selected as a redefinable instruction for purposes of expanding the microprocessor resources available as operands of that instruction.

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