Instruction-programmable processor with instruction loop cache

Details Instruction-programmable processor with instruction loop cache Instruction-programmable processor with instruction loop cache

2005-11-08

2005-11-08

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S042000, C712S233000

Reexamination Certificate

active

06963965

ABSTRACT:
An instruction-programmable processor, such as a digital signal processor, having a level one program cache memory and instruction buffer subsystem, is disclosed. The subsystem includes a loop cache subsystem that includes a branch cache register file for storing instruction opcodes corresponding to a sequence of fetch addresses beginning with a base address. If the fetch address issued by the instruction fetch unit is a hit relative to the loop cache subsystem loop cache control logic disables reads from program data RAM in favor of accesses to the branch cache register file. The branch cache register file can be loaded with opcodes beginning with each backward branch that is a miss relative to the branch cache register file and can be loaded with opcodes beginning with backward branches that are a miss relative to the branch cache register file and that have been executed twice in succession.

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