Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Patent
1998-03-31
2000-01-11
Treat, William M.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
G06F 930
Patent
active
060147350
ABSTRACT:
The present invention discloses a method and apparatus for encoding an instruction in an instruction set which uses a prefix code to qualify an existing opcode of an existing instruction. An opcode and an escape code are selected. The escape code is selected such that it is different from the prefix code and the existing opcode. The opcode, the escape code, and the prefix code are combined to generate an instruction code which uniquely represents the operation performed by the instruction.
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Visual Instruction Set (VIS) User's Guide, Sun Microsystems, Version 1.1, Mar. 1997, pp. i-xii, 1-127.
AMD-3D Technology Manual, Advance Micro Devices, (AMD), Feb. 1998, pp. i-x, 1-58.
Chennupaty Srinivas
Hacking Lance
Huff Thomas
Roussel Patrice L.
Thakkar Shreekant S.
Intel Corporation
Treat William M.
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