Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
2005-10-18
2005-10-18
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S211000
Reexamination Certificate
active
06957321
ABSTRACT:
Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.
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Bacon Shireen I.
Intel Corporation
Tsai Henry W. H.
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