Filter micro-coded accelerator

Finding a significant bit in a computer data word

Fine grained multi-thread dispatch block mechanism

Fixed length memory to memory arithmetic and architecture...

Fixed length memory to memory arithmetic and architecture...

Fixed point unit pipeline allowing partial instruction...

Fixed shift amount variable length instruction stream...

Flag bits evaluation for multiple vector SIMD channels...

Flag optimization of a trace

Flag renaming and flag masks within register alias table

Flags handling for system call instructions

Flexible demand-based resource allocation for multiple...

Flexible digital signal processor

Flexible resource access in a microprocessor

Flexible results pipeline for processing element

Flexible scheduling of non-speculative instructions

Floating point and multimedia unit with data type reclassificati

Floating point exception handling in pipelined processor...

Floating point NaN comparison

Floating point only SIMD instruction set architecture...