Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-08-23
2011-08-23
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
08006067
ABSTRACT:
A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighborhood connection register configured to receive data from and send data to other processing elements. The connections between the result registers and between the result registers and the neighborhood connection register are selectively configurable by applied control signals.
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Dorsey & Whitney LLP
Li Aimee J
Micro)n Technology, Inc.
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