Fine grained multi-thread dispatch block mechanism

Details Fine grained multi-thread dispatch block mechanism Fine grained multi-thread dispatch block mechanism

2007-12-25

2007-12-25

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S219000

Reexamination Certificate

active

11154158

ABSTRACT:
The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.

REFERENCES:
patent: 5584031 (1996-12-01), Burch et al.
patent: 6341347 (2002-01-01), Joy et al.
patent: 2006/0031704 (2006-02-01), Hayashi
patent: 2006/0190703 (2006-08-01), Carrie

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