Flag bits evaluation for multiple vector SIMD channels...

Details Flag bits evaluation for multiple vector SIMD channels... Flag bits evaluation for multiple vector SIMD channels...

2007-05-15

2007-05-15

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S005000, C712S222000, C712S224000

Reexamination Certificate

active

11015778

ABSTRACT:
According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by the SIMD execution engine. According to some embodiments, a vertical evaluation unit might perform evaluation operations across multiple flag registers.

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patent: 2002/0083311 (2002-06-01), Paver
patent: 2004/0034760 (2004-02-01), Paver et al.
patent: 2004/0068642 (2004-04-01), Tanaka et al.
patent: 2004/0088521 (2004-05-01), Barlow et al.
patent: 0 682 309 (1995-11-01), None
patent: 2000047998 (2000-02-01), None
“PCT International Search Report of the International Searching Authority”, mailed Oct. 10, 2006, for PCT/US2005/046321, 4pgs.

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