Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2006-02-21
2006-02-21
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
C712S027000
Reexamination Certificate
active
07003648
ABSTRACT:
A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into a plurality of thread processing units (“TPUs”) and allocation logic that monitors each TPUs demand for entries in the store queue. Demand is determined by subtracting an adjustable threshold value from the most recently assigned store identifier value. If the difference between the most recently assigned instruction identifier for a TPU and the TPU's threshold is non-zero, then it is determined that the TPU has demand for at least one entry in the store queue. The allocation logic includes arbitration logic that determines which one of a plurality of TPUs with store queue demand should be allocated a free entry in the store queue.
REFERENCES:
patent: 6112019 (2000-08-01), Chamdani et al.
patent: 6481251 (2002-11-01), Meier et al.
patent: 6738896 (2004-05-01), Webb et al.
Chang Chuan-Hua
Chrysos George Z.
Emer Joel S.
Mylius John H.
Soderquist Peter
Hewlett--Packard Development Company, L.P.
Pan Daniel
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