Multithreaded programmable processor and system with...
Multithreading processor with thread predictor
N-wide add-compare-select instruction
Native copy instruction for file-access processor with...
Near-orthogonal dual-MAC instruction set architecture with...
Network processor which makes thread execution control...
Networked processor for a pipeline architecture
Non-blocking, multi-context pipelined processor
Non-destructive sideband reading of processor state information
Non-speculative instruction fetch in speculative processing
Number of pipeline stages and loop length related counter differ
Operand queues for streaming data: A processor register file...
Operating system device centric agent
Operating system thread scheduling for optimal heat dissipation
Operation, compare, branch VLIW processor
Optimized branch predictions for strongly predicted compiler...
Optimizing cache data load required for functions in loop...
Out-of-order execution microprocessor that selectively...
Out-of-order processing with predicate prediction and...
Out-of-pipeline trace buffer for holding instructions that...