Out-of-order execution microprocessor that selectively...

Details Out-of-order execution microprocessor that selectively... Out-of-order execution microprocessor that selectively...

2008-11-25

2011-12-06

Li, Aimee (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S023000

Reexamination Certificate

active

08074060

ABSTRACT:
A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result. The retire unit makes the determination before the execution unit outputs the result of the non-excepting type instruction, wherein the retire unit makes the determination after the execution unit outputs the result of the excepting type instruction.

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