Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1998-09-21
2001-06-12
Follansbee, John A. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S032000, C712S216000, C712S228000, C712S233000, C712S237000, C712S238000, C712S239000, C712S240000, C709S241000
Reexamination Certificate
active
06247121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to processors and, more particularly, to creation and management of threads in a processor.
2. Background Art
Current superscaler processors, such as a microprocessor, perform techniques such as branch prediction and out-of-order execution to enhance performance. Processors having out-of-order execution pipelines execute certain instructions in a different order than the order in which the instructions were fetched and decoded. Instructions may be executed out of order with respect to instructions for which there are not dependencies. Out-of-order execution increases processor performance by preventing execution units from being idle merely because of program instruction order. Instruction results are reordered after execution.
The task of handling data dependencies is simplified by restricting instruction decode to being in-order. The processors may then identify how data flows from one instruction to subsequent instructions through registers. To ensure program correctness, registers are renamed and instructions wait in reservation stations until their input operands are generated, at which time they are issued to the appropriate functional units for execution. The register renamer, reservation stations, and related mechanisms link instructions having dependencies together so that a dependent instruction is not executed before the instruction on which it depends. Accordingly, such processors are limited by in-order fetch and decode.
When the instruction from the instruction cache misses or a branch is mispredicted, the processors have either to wait until the instruction block is fetched from the higher level cache or memory, or until the mispredicted branch is resolved, and the execution of the false path is reset. The result of such behavior is that independent instructions before and after instruction cache misses and mispredicted branches cannot be executed in parallel, although it may be correct to do so.
Multithreading processors such as shared resource multithreading processors and on-chip multiprocessor (MP) processors have the capability to process and execute multiple threads concurrently. The threads that these processors process and execute are independent of each other. For example, the threads are either from completely independent programs or are from the same program but are specially compiled to create threads without dependencies between threads. However, these processors do not have the ability to concurrently execute different threads from the same program that may have dependencies. The usefulness of the multithreading processors is thereby limited.
Accordingly, there is a need for multithreading processors that have the ability to concurrently execute different threads from the same program where there may be dependencies among the threads.
SUMMARY OF THE INVENTION
In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction.
The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction.
The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.
REFERENCES:
patent: 5142634 (1992-08-01), Fite et al.
patent: 5153848 (1992-10-01), Elkind et al.
patent: 5309561 (1994-05-01), Overhouse et al.
patent: 5313634 (1994-05-01), Eickemeyer
patent: 5420990 (1995-05-01), McKeen et al.
patent: 5421021 (1995-05-01), Saini
patent: 5524250 (1996-06-01), Chesson et al.
patent: 5524262 (1996-06-01), Colwell et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5586278 (1996-12-01), Papworth et al.
patent: 5588126 (1996-12-01), Abramson et al.
patent: 5606670 (1997-02-01), Abramson et al.
patent: 5613083 (1997-03-01), Glew et al.
patent: 5664137 (1997-09-01), Abramson et al.
patent: 5724565 (1998-03-01), Dubey et al.
patent: 5742782 (1998-04-01), Ito et al.
patent: 5754818 (1998-05-01), Mohamed
patent: 5802272 (1998-09-01), Sites et al.
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5832260 (1998-11-01), Arora et al.
patent: 5881280 (1999-03-01), Gupta et al.
patent: 5887166 (1999-03-01), Mallick et al.
patent: 5933627 (1999-08-01), Parady
patent: 5961639 (1999-10-01), Mallick et al.
M. Franklin, “The Multiscalar Architecture,” Ph.D. Dissertation, Univ. of Wisconsin, 1993, pp. i, ii, v-ix, 50-73, 75-81, 86-107, and 153-161.
M. Franklin et al., ARB: A Hardware Mechanism for Dynamic Reordering of Memory References, IEEE Transactions on Computers, vol. 45, No. 5, May 1996, pp. 552-571.
E. Rotenberg et al., “Trace Processors,” The 30th International Symposium on Microarchitecture, Dec. 1997, pp. 138-148.
J. Smith et al., “The Microarchitecture of Superscaler Processors,” Proceedings of the IEEE, vol. 83, No. 12, Dec. 1995, pp. 1609-1624.
G. Sohi et al., “Multiscalar Processors”. The 22nd Annual International Symposium on Computer Architecture, Jun. 1995, pp. 414-425.
P. Song, “Multithreading Comes of Age,” Microprocessor Report, Jul. 14, 1997, pp. 13-18.
J. Tsai et al., “The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation,” Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, Oct. 1996, pp. 35-46.
D. Tullsen et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” The 22nd International Symposium on Computer Architecture, Jun. 1995, pp. 392-403.
U.S. application No. 08/746,547, filed Nov. 13, 1996, pending, “Processor Having Replay Architecture,” Inventor David Sager.
J.C. Steffan et al., “The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization,” 4th International Symposium on High performance Computer Architecture—HPCA-4, pp. 2-13, Jan. 1998.
S. Gopal et al., “Speculative Versioning Cache,” 4th International Symposium on High-Performance Computer Architecture—HPCA-4, pp. 195-205, Jan. 1998.
P. Marcuello et al., “Speculative Multithreading Processors,” Proceedings of the ACM International Conference on Supercomputing 98, Jul. 1998, pp. 77-84.
N. Gloy et al., “An Analysis of Dynamic Branch Preduction Schemes on System Workloads,” Proceedings, 23rd Annual International Symposium on Computer Architecture, May 1996, pp. 12-21.
S. McFarling, “Combining Branch Predictors,” WRL Technical Note TN-36, Wetern Research Laboratory, Jun. 1993, pp. 1-20.
Q. Jacobson et al. “Path-Based Next Trace Prediction,” Proceedings of the 30th International Symposium on Microarchitecture, Dec. 1997, pp. 14-23.
Q. Jacobson et al. “Control Flow Speculation in Multiscalar Processors,” Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, Feb. 1997, pp. 218-229.
R. Nair, “Dynamic path-based branch correlation,” Proceedings of the 28th International Symposium on Microarchitecture, Dec. 1995, pp. 15-23.
S. Palacharla et al., “Complexity-Effective Superscalar Processors,” The 24th Annual Interna
Akkary Haitham
Jacobson Quinn A.
Aldous Alan K.
Follansbee John A.
Intel Corporation
Nguyen Dzung C
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