Non-blocking, multi-context pipelined processor

Details Non-blocking, multi-context pipelined processor Non-blocking, multi-context pipelined processor

2006-07-18

2006-07-18

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S001000

Reexamination Certificate

active

07080238

ABSTRACT:
A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

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