Networked processor for a pipeline architecture

Details Networked processor for a pipeline architecture Networked processor for a pipeline architecture

2011-01-25

2011-01-25

Lee, Chun-Kuan (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S225000, C708S209000

Reexamination Certificate

active

07877581

ABSTRACT:
A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

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