Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2006-08-15
2006-08-15
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C718S107000
Reexamination Certificate
active
07093109
ABSTRACT:
A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.
REFERENCES:
patent: 5251205 (1993-10-01), Callon et al.
patent: 5327526 (1994-07-01), Nomura et al.
patent: 5353418 (1994-10-01), Nikhil et al.
patent: 5357617 (1994-10-01), Davis et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5404560 (1995-04-01), Lee et al.
patent: 5483641 (1996-01-01), Jones et al.
patent: 5499349 (1996-03-01), Nikhil et al.
patent: 5560029 (1996-09-01), Papadopoulos et al.
patent: 5613114 (1997-03-01), Anderson et al.
patent: 5742782 (1998-04-01), Ito et al.
patent: 5752031 (1998-05-01), Cutler et al.
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5826081 (1998-10-01), Zolnowsky
patent: 5887166 (1999-03-01), Mallick et al.
patent: 5907702 (1999-05-01), Flynn et al.
patent: 5913059 (1999-06-01), Torii
patent: 5933627 (1999-08-01), Parady
patent: 5944816 (1999-08-01), Dutton et al.
patent: 5968167 (1999-10-01), Whittaker et al.
patent: 6016542 (2000-01-01), Gottlieb et al.
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6067565 (2000-05-01), Horvitz
patent: 6341347 (2002-01-01), Joy et al.
patent: 6658447 (2003-12-01), Cota-Robles
patent: 6931641 (2005-08-01), Davis et al.
Kruse and Ryba, “Data Structures And Program Design in C++,” 1999, pp. 153, 369-370, 444-445.
Hennessy and Patterson, “Computer Architecture—A Quantitative Approach, 2ndEdition,” 1996, p. 40.
Fiske et al., “Thread Priorization : A Thread Scheduling Mechanism For Multiple-Context Parallel Processors,” Jan. 1995□□.
Weiss, Data Structures & Algorithm Analysis in C++, 2nd Edition, 1999, pp. 211-212.
Davis Gordon Taylor
Heddes Marco C.
Leavens Ross Boyd
Verplanken Fabrice Jean
Chan Eddie
Cockburn Joscelyn G.
Huisman David J.
International Business Machines - Corporation
Lucas James A.
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