High-throughput interface between a system memory controller...

Holding mechanism for changing operation modes in a pipelined co

Hybrid branch prediction device with two levels of branch...

Hybrid branch prediction using a global selection counter...

Hybrid branch predictor having negative ovedrride signals

Hybrid branch predictor with improved selector table update...

Identification and correction of cyclically recurring errors...

Identifying and processing essential and non-essential code...

Implementation of a conditional move instruction in an...

Implementation of an efficient instruction fetch pipeline...

Implementation of variable length instruction encoding using...

Implementing software breakpoints and debugger therefor

In-circuit emulator with internal trace memory

In-line code suppression

Incorporating local branch history when predicting multiple...

Incorporating trigger loads in branch histories for branch...

Increasing general registers in X86 processors

Increasing the overall prediction accuracy for multi-cycle...

Indexed table circuit having reduced aliasing

Indexing branch target instruction memory using target...