In-circuit emulator with internal trace memory

Details In-circuit emulator with internal trace memory In-circuit emulator with internal trace memory

1998-08-13

2001-05-15

Lee, Thomas (Department: 2782)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C714S028000, C714S029000, C714S033000

Reexamination Certificate

active

06233673

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an in-circuit emulator (abbreviated to ICE from now on) that has an observing function of CPU input/output port signals and an execution control function of programs, for supporting debugging of a system equipped with a CPU.
2. Description of Related Art
FIG. 6
is a block diagram showing a configuration of a conventional ICE together with an internal configuration of an ICE CPU. In
FIG. 6
, the reference numeral
1
designates an ICE;
2
designates an ICE CPU embedded in the ICE
1
; and
3
designates an external trace memory provided outside the ICE CPU
2
for tracing signal logic on input/output ports of the ICE CPU
2
. The reference numeral
4
designates an ICE controller for carrying out the execution control of the ICE CPU
2
, the control of the external trace memory
3
and the interface with terminal equipment not shown in this figure;
5
designates a processor probe consisting of a cable for connecting the ICE
1
to connection ports of a system board to be debugged; and
6
designates a CPU bus for interconnecting the external trace memory
3
, ICE controller
4
and processor probe
5
.
In the ICE CPU
2
, the reference numeral
11
designates a CPU core
11
constituting a kernel of the ICE CPU
2
;
12
designates an internal execution controller for controlling the operation of the CPU core
11
; and
13
designates a CPU internal signal output circuit for outputting the internal state of the CPU core
11
.
Next, the operation of the conventional ICE will be described.
The CPU core
11
in the ICE CPU
2
is a CPU for carrying out the same operation as that of the CPU on a system board to be debugged. To use the ICE
1
, the CPU on the system board is removed, and the input/output ports of that CPU is connected with the ICE
1
via the processor probe
5
. Subsequently, the CPU core
11
of the ICE CPU
2
in the ICE
1
is caused to operate in place of the CPU to be debugged.
In the ICE CPU
2
, the CPU internal signal output circuit
13
supplies, in synchronism with a clock signal, the external trace memory
3
and the ICE controller
4
with the signal logic on the input/output ports of the CPU core
11
, which operates under the execution control of the internal execution controller
12
, as CPU internal signals. The external trace memory
3
samples at every clock interval the signal voltage levels of the CPU internal signals fed from the CPU internal signal output circuit
13
, and stores the sampled results. Using the external trace memory
3
, the ICE
1
implements the observing function of the input/output port signals of the CPU
2
.
Techniques relevant to such a conventional ICE are disclosed in Japanese patent application laid-open Nos. 63-188245/1988 and 2-133834/1990, for example.
In the conventional ICE
1
with such a configuration, the number of the chip terminals of the ICE CPU
2
is restricted, and this presents problems of limiting the number of bits of the CPU internal signals that can be output in parallel, and of making it difficult for the external trace memory
3
to sample at every clock interval the signal waveforms of the CPU internal signals output from the CPU internal signal output circuit
13
, when the operation frequency of the ICE CPU
2
increases.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide an ICE with a trace memory embedded in the ICE CPU, which enables the CPU internal signals to be output in parallel independently of the number of the chip terminals of the ICE CPU, and enables the trace memory to sample the CPU internal signals with ease in spite of a high operation frequency of the ICE CPU.
According to one aspect of the present invention, there is provided an in-circuit emulator for supporting debugging of a debugged system including a CPU, the in-circuit emulator having an observing function of signals on input/output ports of the CPU, and a function of carrying out execution control of a program, the in-circuit emulator comprising: a processor probe for connecting the in-circuit emulator to the input/output ports of the CPU on a board of the debugged system; an in-circuit emulator CPU embedded in the in-circuit emulator for implementing operations equivalent to those of the CPU of the debugged system; and an in-circuit emulator controller for controlling execution processing of the in-circuit emulator CPU, wherein the in-circuit emulator CPU comprises: a CPU core that carries out processing operations equivalent to those of the CPU of the debugged system; an internal trace memory for tracing a CPU internal signal of the CPU core; and a CPU internal signal output circuit for supplying the S trace memory with the CPU internal signal of the CPU core in synchronism with a clock signal.
Here, the in-circuit emulator CPU may further comprise a bit-width converter for converting the CPU internal signal, which is read out of the internal trace memory, into a plurality of reduced bit-width signals, each having a bit number less than that of the CPU internal signal, and supplies them to the in-circuit emulator controller in multiple cycles.
The in-circuit emulator CPU may further comprise an internal execution control circuit for exchanging a signal with the in-circuit emulator controller, and for controlling execution of the processing operations of the CPU core in response to the signal exchanged.
The internal trace memory of the in-circuit emulator CPU may comprise at least two DRAM cell arrays, one of which is preparing for writing, while the other of which is writing.
The in-circuit emulator CPU may further comprise a tracing halt controller for halting writing of the CPU internal signal into the internal trace memory in response to contents of the CPU internal signal fed from the CPU internal signal output circuit.
The in-circuit emulator may further comprise an external signal probe for bringing, as an external signal, into the in-circuit emulator a signal other than signals of the CPU on the board of the debugged system, wherein the CPU internal signal output circuit in the in-circuit emulator CPU may have a function of receiving the external signal through the external signal probe, and supply it to the internal trace memory and the trace halt controller.


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Journal of IPSJ, vol. 38, No. 10, Oct. 1997 (translation of the relevant part JTAG/EJTAG).

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