Implementation of a conditional move instruction in an...

Details Implementation of a conditional move instruction in an... Implementation of a conditional move instruction in an...

1998-11-18

2002-09-10

Maung, Zarni (Department: 2154)

Electrical computers and digital processing systems: processing

Processing control

Branching

C717S155000

Reexamination Certificate

active

06449713

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to data processing and in particular to techniques for processing a conditional move instruction within a data processor.
BACKGROUND OF THE INVENTION
In general, data processors are capable of executing a variety of instructions. one type of instruction is called a conditional move instruction. From a programmer's perspective, a typical conditional move instruction instructs a processor to test whether a particular condition exists (e.g., whether a particular register stores zero), and to move information into a destination register if the particular condition exists. If the
 
CMOVXX S
—
R
A
, S
—
R
E
, D
—
R
C
,
where “CMOVXX” indicates that the instruction is a conditional move instruction that tests for a condition “XX”. “S_R
A
” and “S_R
B
” are source operands that respectively identify registers R
A
and R
B
. “D_R
C
” is a destination operand that identifies register R
C
.
In general, how a processor uses registers depends on whether the processor is capable of executing instructions out of program order. For a processor that cannot execute instructions out of program order (i.e., an in-order processor), instruction source and destination operands typically identify physical registers within the processor. The pseudo-code for executing the CMOVXX instruction in an in-order processor is as follows:
if (
XX
(
R
A
)), then
R
C
=R
B
.
According to the pseudo-code, the processor determines whether a condition XX exists involving physical register R
A
(e.g., whether physical register R
A
stores zero). If the condition XX exists, the processor moves the contents of physical register R
B
into physical register R
C
. Otherwise, the processor leaves the original contents of physical register R
C
unaltered.
In a processor that is capable of executing instructions out of program order (i.e., an out-of-order processor), instruction source and destination operands typically identify logical registers instead of the physical registers directly. The out-of-order processor maps these logical registers to physical processor registers just before instruction execution such that the result of each instruction is stored in a new physical register. This approach enables the processor to avoid problems when executing instructions out of program order (e.g., read-after-write data hazards).
The pseudo-code for executing a CMOVXX instruction in an out-of-order processor is therefore somewhat more complex. Suppose that, prior to mapping the CMOVXX instruction, the out-of-order processor maps logical register R
A
to physical register R
A1
, logical register R
B
to physical register R
B1
, and logical register R
C
to physical register R
C1
. Additionally suppose that, after mapping the CMOVXX instruction, the out-of-order processor maps logical register R
C
to physical register R
C2
(an new physical register). The pseudo-code for executing the CMOVXX instruction in such a processor is therefore as follows:
if (
XX
(
R
A1
)), then
R
C2
=R
B2
else
R
C2
=R
C1
.
According to the pseudo-code, the out-of-order processor determines whether a condition XX exists involving physical register R
A1
(logical register R
A
) If the condition XX exists, the processor moves the contents of physical register R
B1
(logical register R
B
) into physical register R
C2
(to which logical register R
C
presently is mapped). As such, the contents of logical register R
B
are stored in logical register R
C
. If the condition XX does not exist, the processor moves the contents of physical register R
C1
(to which logical register R
C
previously was mapped) into physical register R
C2
such that a programmer perceives the contents of logical register R
C
as remaining unaltered.
SUMMARY OF THE INVENTION
When a processor executes an instruction within an instruction stream, an execution circuit (or unit) of the processor receives instruction data through input ports, and executes the instruction according to the instruction data. For example, an execution unit of an in-order processor may execute the conditional move instruction:
CMOVXX S
—
R
A
, S
—
R
B
, D
—
R
C
according to the pseudo-code:
if (
XX
(
R
A
)), then
R
C
=R
B
where R
A
, R
B
and R
C
refer to physical registers within the in-order processor. To receive instruction data used by the CMOVXX instruction, the execution unit requires only two input ports: a first port to receive the contents of physical register R
A
, and a second port to receive the contents of physical register R
B
.
However, an execution unit of an out-of-order processor executes the CMOVXX instruction according to the following pseudo-code:
if (
XX
(
R
A1
)), then
R
C2
=R
B1
else
R
C2
=R
C1
where R
A1
, R
B1
, R
C1
and R
C2
refer to physical registers within the in-order processor. To implement this instruction, the out of order execution unit requires three input ports: a first port to receive the contents of physical register R
A1
, a second port to receive the contents of physical register R
B1
, and a third port to receive the contents of physical register R
C1
.
There are disadvantages to a processor that uses three input ports to execute instructions. In particular, such a processor would require substantial semiconductor resources (e.g., a disproportionately large area for input port routing). Additionally, processors typically use no more than two input ports to execute non-conditional move instructions. Accordingly, processor designers generally prefer to limit the number of input ports for each instruction to no more than two. Unfortunately, as explained above, a conventional implementation the CMOVXX instruction within an out-of-order processor uses three input ports.
In contrast, an embodiment of the present invention is directed to a technique for handling a conditional move instruction in an out-of-order data processor. The technique involves detecting a conditional move instruction within an instruction stream, and generating multiple instructions according to the detected conditional move instruction. The technique further involves replacing the conditional move instruction within the instruction stream with the generated multiple instructions. Preferably, each of the generated multiple instructions executes using no more than two input ports. As such, it is unnecessary for the processor to use three input ports to execute the instructions.
The generation of multiple instructions preferably involves providing a first generated instruction that determines whether a condition exists, and providing a second generated instruction that performs a move operation based on whether the condition exists. In particular, the second generated instruction performs a first move operation when the condition is determined to exist, and a second move operation when the condition is determined not to exist. When the condition exists, the first move operation loads a new physical register with contents from a specified source register so that, from a programmer's perspective, the processor alters a logical register mapped to the new physical register. When the condition does not exist, the second move operation loads the new physical register with contents of a previously used physical register (to which the logical register was previously mapped) so that, from the programmer's perspective, the processor leaves the logical register unaltered.
Instruction generation may involve providing a first generated instruction that produces a condition result, and providing a second generated instruction that (i) inputs the condition result from a first portion of a register that is separate from a second portion that stores standard contents of the register, and (ii) performs an operation according to the first portion. To this end, the mechanisms for storing the condition result and the standard contents are treated as a single entity (e.g., a register with an extra bit field to store the condition result) rather than as separate registers. As such, the same circ

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