Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
2006-01-13
2008-10-14
Dollinger, Tonia L. M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S207000, C712S229000, C712S244000, C712S001000, C717S126000, C717S128000, C717S131000
Reexamination Certificate
active
07437542
ABSTRACT:
A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.
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Amendment and Response Dec. 2, 2003.
Non-Final OA Sep. 4, 2003.
Amendment and Response Mar. 18, 2005.
Amendment and Response Aug. 9, 2004.
Amendment and Response Sep. 12, 2005.
Final OA Mar. 8, 2004.
Final OA Jun. 17, 2005.
Non-Final OA Nov. 18, 2004.
Notice of Allowance Oct. 12, 2005.
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Berson David A.
Kling Ralph
Kozuch Michael A.
Lai Konrad
Lee Yong-Fong
Dollinger Tonia L. M.
Intel Corporation
Schwegman Lundberg & Woessner, P.A.
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